View SPT9101_353893.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SPT9101
125 MSPS SAMPLE-AND-HOLD AMPLIFIER
FEATURES
* * * * Second Source of AD9101 350 MHz Sampling Bandwidth 125 MHz Sampling Rate Excellent Hold Mode Distortion -75 dB at 50 MSPS (23 MHz VIN) -62 dB at 100 MSPS (48 MHz VIN) 7 ns Acquisition Time to 0.1% <1 ps Aperture Jitter 66 dB Feedthrough Rejection at 50 MHz Low Spectral Noise Density
APPLICATIONS
* * * * * * Test Instrumentation Equipment RF Demodulation Systems High Performance CCD Capture Digital Sampling Oscilloscopes Commercial and Military Radar High-Speed DAC Deglitching
* * * *
GENERAL DESCRIPTION
The SPT9101 is a high-speed track-and-hold amplifier designed for a wide range of use. The SPT9101 is capable of sampling at speeds up to 125 MSPS with resolutions ranging from 8 to 12 bits. Trim programmable internal hold and compensation capacitors provide for optimized input bandwidth and slew rate versus noise performance.
The performance of this device makes it an excellent front end driver for a wide range of ADCs on the market today. Significant improvements in dynamic performance can be achieved by using this device ahead of virtually all ADCs that do not have an internal track-and-hold. The SPT9101 is offered in 20-lead SOIC and LCC packages over the industrial temperature range and in die form. Contact the factory for military and /833 package options.
BLOCK DIAGRAM
VIn
Sampler +
CHOLD
+ 4X Amp -
VOUT
R
3R
CLK NCLK
RTN
ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)1
Supply Voltages Supply Voltage (+VS) ................................ -0.5 V to +6 V Supply Voltage (-VS) ................................. -6 V to +0.5 V Input Voltages Analog Input Voltage ................................................ 5 V CLK, NCLK Input ....................................... -5 V to +0.5 V Output Currents Continuous Output Current ................................... 70 mA Temperature Operating Temperature .............................. -40 to +85 C Junction Temperature ......................................... +150 C Lead, Soldering (10 seconds) ............................. +220 C Storage ..................................................... -65 to +150 C
Note 1: Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied conditions in typical application.
ELECTRICAL SPECIFICATIONS
+VS=+5.0 V, -VS=-5.2 V, RLOAD=100 , unless otherwise specified.
PARAMETERS DC Performance Gain VIN = 0.5 V Offset VIN = 0 V Output Resistance Output Short Circuit Current PSRR VS = 0.5 V p-p Pedestal Sensitivity to Pos. Supply VS = 0.5 V p-p Pedestal Sensitivity to Neg. Supply VS = 0.5 V p-p Analog Input/Output Maximum Output Voltage Range6 Input Bias Current Input Capacitance Input Resistance Clock Inputs Input Bias Current Input Low Voltage Input High Voltage Track Mode Dynamics
TEST CONDITIONS +25 C Full Temp. +25 C Full Temp. +25 C Full Temp. +25 C Full Temp. Full Temp.
TEST LEVEL I VI I VI V V VI V V
MIN 3.93 3.9
SPT9101 TYP 4.0 3 0.5 60 43 4 8
MAX 4.07 4.1 10 30
UNITS V/V V/V mV mV mA dB mV/V mV/V
37
Full Temp. +25 C Full Temp. +25 C Full Temp. +25 C Full Temp. Full Temp.
VI I VI V VI VI VI VI IV IV V V V
2.4
2.7 15 2 450 3 -1.8 -0.8 180 1400 55 270 3.9
30 35
100
V A A pF k A V V MHz V/s ns V
nV Hz
30 -1.5
-1.0 150 1100
Bandwidth (-3 dB) VOut = 1.0 V p-p Full Temp. Slew Rate 4 V Output Step Full Temp. Overdrive Recovery Time1 To 0.1% Integrated Output Noise BW = 5 to 200 MHz Input RMS Spectral Noise 10 MHz
SPT9101
2
12/30/99
ELECTRICAL SPECIFICATIONS
+VS=+5.0 V, -VS=-5.2 V, RLOAD=100 , unless otherwise specified.
PARAMETERS Hold Mode Dynamics Worst Harmonic VOut = 2 V p-p Worst Harmonic VOut = 2 V p-p Worst Harmonic VOut = 2 V p-p Worst Harmonic VOut = 2 V p-p Sampling Bandwidth2 VIN = 0.5 V p-p Hold Noise3 (RMS) Droop Rate Feedthrough Rejection (50 MHz) VOut = 2 V p-p Maximum Hold Time, VIN=0 V Track-and-Hold Switching Aperture Delay Aperture Jitter Pedestal Offset, VIN=0 V Transient Amplitude Settling Time to 4 mV Glitch Product4 VIN = 0 V Hold-to-Track Switching Acquisition Time to 0.1% 2 V Output Step Acquisition Time to 0.01% 2 V Output Step Power Supply5 +VS Voltage -VS Voltage Power Dissipation
TEST CONDITIONS 23 MHz, 50 MSPS +25 C 48 MHz, 100 MSPS +25 C 48 MHz, 100 MSPS Full Temp. 48 MHz, 125 MSPS +25 C -3 dB, +25 C +25 C VIN=0.0 V, +25 C Full Temp. Full Temp. +25 C +25 C +25 C Full Temp. VIN = 0 V, Full Temp. Full Temp. +25 C
TEST LEVEL V IV IV V V V V V IV V V I VI V V V
MIN
SPT9101 TYP -75 -62
MAX
UNITS dB FS
-57 -53
dB FS dB FS dB FS MHz mV/s mV/s dB ns ps ps rms mV mV mV ns pV-s
-57 350 150 x tH -40 -66 100 200 -250 <1 10 8 4 20
25 35
+25 C +25 C Full Temp. Full Temp, Track Mode Full Temp, Clocked Mode Full Temp, Track Mode Full Temp, Clocked Mode Full Temp, Track Mode Full Temp, Clocked Mode
V IV IV VI VI VI VI VI VI
7 11 14 16 65 55 65 55 663 561
ns ns ns mA mA mA mA mW mW
54 44 54 44 551 449
1 Time to recover within rated error band from 160% overdrive. 2 Sampling bandwidth is defined as the -3 dB frequency response of the input sampler to the hold capacitor when operating in the
sampling mode. It is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier.
3 Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (tH) is 20 ns, the accumulated
noise is typically 3 V (150 mV/s x 20 ns). This value must be combined with the track mode noise to obtain total noise. Typical thermal impedances:
4 Total energy of worst case track-to-hold or hold-to-track glitch.
JC (LCC) = +6 C/W JA (SOIC) = +85 C/W in still air at +25 C ambient. 5Clocked mode is specified with a 50% clock duty cycle. 6Analog input voltage should be limited 0.8 volts to maintain device in linear range.
SPT9101
3
12/30/99
TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/ max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 C. Parameter is guaranteed over specified temperature range.
Figure 1 - Timing Diagram
Input Acquisition Time Observed at Hold Capacitor
Aperature Delay
Output Observed at Amplifier Output Track-to-Hold Settling
CLK
Hold
Track
Hold
NCLK
TIMING SPECIFICATION DEFINITIONS
ACQUISITION TIME This is the time it takes the SPT9101 to acquire the analog signal at the internal hold capacitor when it makes a transition from hold mode to track mode. (See figure 1.) The acquisition time is measured from the 50% input clock transition point to the point when the signal is within a specified error band at the internal hold capacitor (ahead of the output amplifier). It does not include the delay and settling time of the output amplifier. Because the signal is internally acquired and settled at the hold capacitor before the output voltage has settled, the sampler can be put in hold mode before the output has settled.
TRACK-TO-HOLD SETTLING TIME The time required for the output to settle to within 4 mV of its final value. APERTURE DELAY The aperture delay time is the interval between the leading edge transition of the clock input and the instant when the input signal was equal to the held value. It is the difference in time between the digital hold switch delay and the analog signal propagation time. Because the analog propagation time is longer than the digital delay in the SPT9101, the aperture delay is a negative value.
SPT9101
4
12/30/99
Figure 2 - Typical Interface Circuit
+ +A5 12 13 17 18 4 5 8 9 2.2 F -A5.2 + 2.2 F NOTES: 1) Vt = Threshold voltage: a) For TTL or CMOS Clock input +A5
+VS
+VS
+VS
-VS
-VS
+VS
-VS
-VS
3k
1k
VIN
15
VIN
SPT9101
RTN 1,2 CLK NCLK 10 11 GND
VOUT
18
Vt b) For ECL Clock input
VOUT
-A5.2
3k Vt
1k
6,7,16
2) Unless otherwise specified, all capacitors are 0.01 or 0.1 F, surface mount. 3) X = Termination (if required).
+A5
-A5.2
330 -A5.2
330
-A5.2
4) CLKIN a) TTL/CMOS CLKIN R R 96850
2 3
220 VCC 8 VEE GND 1,16 11
220
CLK IN
Vt
X
4
IN+
SPT, HCMP96850 INLE 6 12 b) ECL: Direct Input
THEORY OF OPERATION
The SPT9101 is a monolithic 125 MSPS track and hold amplifier built on a very high-speed complementary bipolar process. It is pin and functionally compatible with the AD9101. It is a two stage design with a sampler driving a hold capacitor followed by a noninverting output buffer amplifier with gain of 4. The first stage sampler is based on a current amplifier in noninverting gain of one configuration with inverting input connected to the output. The hold switch is integrated into this closed-loop first stage amplifier. The output buffer amplifier is in a noninverting gain of 4 configuration with inverting input connected to a resistor divider driven from the output. The noninverting input from the hold capacitor employs input bias current cancellation which results in excellent droop rate performance. The sampler and amplifier stages both employ complementary current amplifiers for high-speed, low-distortion performance.
CLOCK DRIVER CIRCUIT (CLK, NCLK PINS) Fairchild highly recommends that a differential ECL clock be used to drive the SPT9101. Both the 10KH and 100KH family of ECL logic can be used. The typical interface diagram, figure 2, shows the use of a SPT HCMP96850 high-speed comparator. The comparator has a typical propagation delay of 2.4 ns, very low offset of 3 mV, and a minimum tracking bandwidth of 300 MHz. The comparator shown has been set up in a feedthrough operation mode with latch enable connected to a logic high. The threshold voltage (Vt) can be set using a resistor divider as shown in note 1 of figure 2. The configuration shown in note 1a is for a TTL/CMOS clock input and the configuration shown in note 1b is for an ECL clock input. The differential output of the comparator is directly fed to the SPT9101 clock input. The comparator can also be driven with a sinewave input, with the threshold voltage (Vt) adjusted to produce the desired track/hold duty cycle ratio. Note 4a shows the resistor divider configuration for a TTL/ CMOS clock input. If an ECL clock is used it can be directly fed into the comparator. OUTPUT LEVEL SHIFTING (RTN PIN) The RTN pin is tied to the output buffer amplifier internal feedback resistor network as shown in the block diagram. Normally this pin is tied to ground for a 4x gain output amplifier configuration. However, this pin may be configured in other ways as long as certain guidelines are met.
TYPICAL INTERFACE CIRCUIT
BOOTSTRAP CAPACITOR The SPT9101 does not require the bootstrap capacitor that is required on the AD9101 between pins 3 and 19. Because pins 3 and 19 are No Connects on the SPT9101, it will work well in existing AD9101 sockets.
SPT9101
5
12/30/99
The RTN pin may be tied to an external voltage to generate an offset at the output. VOut must be kept to less than 2.7 V typical output swing. VOut, with an external reference voltage at the RTN pin, is represented by the following formula: VOut = 4 VIN - 3 VRef where VRef = voltage at RTN pin and | VOut | 2.7 V The following options are generally not recommended due to the possibility of degraded noise performance of the device: the RTN pin can also be tied to an external resistor to reduce the gain but performance may degrade due to increased noise from the external resistor. Also RTN can be left open for unity gain mode, however, noise will increase. In all cases, VIN must be kept to -0.5 V VIN +0.5 V for rated performance.
SAMPLER FOR 12-BIT ADC APPLICATION The SPT9101 was specifically designed for applications where improved bandwidth performance is required. Figure 3 shows as simple block diagram of the SPT9101 as a sampler ahead of the SPT7922 12-bit, 30 MSPS ADC. Figure 3 - Sampler for 12-Bit ADC
VIN
SPT9101
SPT7922
12
Clock 1
Clock 2
The graph below entitled Improved Dynamic Performance Using the SPT9101 shows the performance with and without the SPT9101. The SPT9101 significantly extends the dynamic performance range of the converter.
PERFORMANCE CHARACTERISTICS
Droop Rate vs Temperature
-65
40 0
SPT9101 Hold Mode Distortion vs. Temperature
Input Frequency = 50 MHz Clock Frequency = 100 MHz Hold = 4 ns Track = 6 ns
mV/us
-40 -80 -120 -20 0 20 Temperature (C) 40 60 80
dB
Worst Harmonic
-60 -50
-25
0
25 Temperature (C)
50
75
100
SPT9101 Hold Mode Distortion vs Input Frequency
-75
Improved Dynamic Performance Using the SPT9101
70
-70
Worst Harmonic
SPT9101 & SPT7922
TDE (dB)
60
dB
-65 Clock Frequency = 100 MHz Track = 6 ns Hold = 4 ns
-60
50
SPT7922
(FS = 28 MSPS)
-55 1 10 Input Frequency (MHz) 100
40
5
10 FIN (MHz)
15
20
SPT9101
6
12/30/99
PACKAGE OUTLINES
20-Lead LCC
INCHES MAX .040 typ 0.045 0.345 0.054 0.022 .050 typ 0.055 0.360 0.066 .020 typ 0.028 0.075 1.14 8.76 1.37 0.56 MILLIMETERS MIN MAX 1.02 1.27 1.40 9.14 1.68 0.51 0.71 1.91
A
H
SYMBOL A B C D E F G H
MIN
G
B
Bottom View
Pin 1
C D
F
E
20-Lead SOIC
INCHES MIN MAX 0.291 0.394 0.496 0.050 typ 0.014 0.004 0.093 0.009 0.016 . 0.299 0.419 0.512 0.019 0.012 0.104 0.013 0.050 MILLIMETERS MIN MAX 7.40 10.00 12.60 1.27 typ 0.35 0.10 2.35 0.23 0.40 7.60 10.65 13.00 0.49 0.30 2.65 0.32 1.27
SYMBOL
20
AB
A B C D E F G H I
1
C G F D E H I
SPT9101
7
12/30/99
PIN ASSIGNMENTS
RTN RTN N/C +VS +VS GND GND +VS +VS CLK
1 2 3 4 5 20 19 18 17 16
PIN FUNCTIONS
VOut N/C -VS -VS GND VIn N/C -VS -VS NCLK
SOIC
6 7 8 9 10 15 14 13 12 11
Name RTN +VS GND CLK NCLK -VS N/C VIN VOUT
I/O I I I I I I I O
Function Gain Set Resistor Return +5 V Power Supply Ground True ECL T/H Clock Complement ECL T/H Clock -5.2 V Power Supply No Connection Analog Signal Input Analog Signal Output
VOut
20
RTN
RTN
N/C
N/C
19
2
1
3
-VS -VS GND VIN N/C
18 17 16 15 14
13 12 11 10 9
4
LCC (Bottom View)
5 6 7 8
+VS +VS GND GND +VS
NCLK
CLK
ORDERING INFORMATION
PART NUMBER SPT9101SIS SPT9101SIC SPT9101SCU PACKAGE TYPE 20L SOIC 20L LCC Die* TEMPERATURE RANGE -40 to +85 C -40 to +85 C +25 C
*Please see die specification for guranteed electrical performance.
-VS -VS
+VS
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
www.fairchildsemi.com
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) Copyright 2002 Fairchild Semiconductor Corporation
SPT9101
8
12/30/99

▲Up To Search▲

Price & Availability of SPT9101

	To Download SPT9101 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .